1. Field of the Invention
The present disclosure relates to load sensing of a voltage charge pump system.
2. Description of Related Art
Phase change memory (PCM) is a non-volatile semiconductor memory technology that exploits the reversible switching of certain chalcogenide materials between stable states having very different resistivities. A one-bit PCM cell may be characterized by two stable states: a reset state “1”, corresponding to a fully amorphous state having a high resistance, and a set state “0”, corresponding to a fully (poly-) crystalline state having a low resistance. More recently, a two-bit PCM cell has been developed with four distinct intermediary states of the chalcogenide material, corresponding to different degrees of partial crystallization that yield two distinct intermediary values of resistance between that of the high resistance of the fully amorphous state and that of the low resistance of the fully (poly-) cyrstalline state.
A PCM array requires a number of DC voltages to be generated on a CMOS semiconductor device, including standard CMOS logic (˜1V), bitline pre-charge (˜0.4V), and wordline, read sense and write to bitline (˜2.5 to 4V). Typically, voltages higher than that of the external power supply of the CMOS semiconductor device, ˜1V, are generated on chip by voltage charge pump circuits. In particular, voltage tolerances are critical for resistance sensing during read operations of PCM cells and for bitline write operations. The amount of current that must be supplied for any of the DC voltages varies greatly as a function of the operating mode and the state of each of the PCM cells in the PCM array.
FIG. 1 illustrates a conventional N-stage voltage charge pump 100 including a supply voltage VDD; N voltage charge pump stages 110, 120, 130, 140, each including a switch S, a pumping capacitor C and a clock VCLK, typically cycling between ground and VDD; and an output stage 150, which includes an output load represented by a current generator IL 156 and a load capacitor CL 153. During the initial clock phase, the odd switches, e.g., S1 and S3, are closed and the even switches, e.g., S2, are open, connecting the top plate of C in, for example, the first stage 110 to VDD, while the bottom plate of C is connected to the ground. In the next clock phase, the switches change states, i.e., switches S1 and S3 are open and S2 is closed. The clock in the first stage now equals VDD and part of the charge stored on C in the first phase is transferred to C in the second stage through closed switch S2, where the bottom plate of C in the second stage is now connected to the clock equaling ground. Over both clock phases, each pumping capacitor C receives an amount of charge from the pumping capacitor to its left and transfers a part of this charge to the pumping capacitor on its right.
Typically, a regulator controls a voltage charge pump, such that the voltage charge pump is turned off when the voltage supplied to the load exceeds a target voltage. Similarly, the voltage charge pump is turned on when the regulator detects that the voltage supplied to the load has fallen beneath the target voltage. In this way, the regulator enables the voltage charge pump to supply current to the load at a voltage that is equal to or approximately equal to the target voltage.
However, over time, a sensed voltage of the load of a voltage charge pump will continuously rise above and fall below the target voltage, because current is supplied to the load from the last pumping capacitor only during the clock phase when the switch SOUT is closed and is drained by the load current, IL, when SOUT is open. Thus, current is supplied to the load from the voltage charge pump as discrete pulses of charge into the load. The load, which typically includes a load capacitance and a load current that varies with time, rises in voltage due to the contribution of charge to the load capacitance from the voltage charge pump and then falls at some rate determined by the load current. As a result, the sensed voltage of the load continuously rises above and falls below the target voltage, even if the load current is assumed to be a constant. This rise and fall of the sensed voltage is called ripple, where the amplitude of the ripple about the target voltage is determined by the amount of charge supplied by each pulse of the voltage charge pump, the load capacitance, and the load current.
Load current is a significant design factor in determining the amount of charge that is supplied by the voltage charge pump with each pulse. The design of a conventional voltage charge pump system that supplies a large current load with some ripple, will have a larger amount of ripple when supplying a smaller current load, that is, the amount of voltage ripple is inversely related to the amount of current load. Thus, the problem is to design a voltage charge pump system that produces no greater ripple when supplying a smaller current load, than when supplying a large current load.
Referring to FIG. 2, as illustrated by the voltage versus time graph 200 of a conventional voltage charge pump that produces a fixed amount of current with each pulse of the voltage charge pump to a fixed load capacitance, a small load current is typically associated with a relatively large amplitude of voltage ripple and overshoot at a relatively high time-averaged voltage across the fixed load capacitance 220, while a large load current is typically associated with a relatively small amplitude of voltage ripple and overshoot at a relatively low time-averaged voltage across the fixed load capacitance 240.
In addition, conventional voltage charge pumps, using integrated circuits, cannot easily mitigate the problem of voltage ripple with large load currents with a large decoupling capacitor, because the integrated circuit technology limits the value of the decoupling capacitor due to the large area and high voltage levels required. Large capacitors may impact die size, efficiency and performance of the integrated circuits, while large 3-dimensional capacitors may not be available for non-volatile memory technologies. Power supply transition requirements may also constrain a large decoupling capacitance, and potentially long write cycles may further increase the required size of a decoupling capacitance.
There remains a need for a voltage charge pump scheme that provides improved voltage regulation across a load with small voltage ripple and overshoot to varying load currents without a large decoupling capacitance.